Detect hardware architecture failures before boards are built.
Architon verifies system-level interactions like power budgets, voltage domains, and shared buses. It complements ERC, DRC, and SPICE by catching integration risks that occur between them.
Example architecture finding
Architon prints deterministic, explainable failures with remediation hints. This is the real output format.
How it works
A simple workflow designed for engineers. No new GUI. No lock-in.
1) Ingest
Validate YAML architecture profiles today. KiCad BOM ingestion is in progress.
2) Analyze
Build a system-level model (DesignIR) and run deterministic rules across power, logic levels, and buses.
3) Report
Emit explainable findings for humans and stable exit codes for CI.
rv check examples/mobile-robot-problem.yaml
rv scan bom.csv # coming soonWhat Architon is and is not
Architon complements
ERC, DRC, and SPICE. Those tools validate schematics, layout, and analog behavior. Architon validates system integration logic between components.
Architon does not replace
Electrical rule checks, board-level design rules, or circuit simulation. It focuses on architecture correctness: the interactions that cause failures during bring-up.
Deterministic by default
Same input yields the same output. Findings are explainable with root cause and remediation hints. No probabilistic scoring.